1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and, more particularly, to an image sensing device.
2. Description of the Related Art
In general, an image sensing device refers to a device that captures an image by using a semiconductor with properties that respond to incident light. Charge Coupled Device (CCD) technology has been widely used for image sensing devices. However, as Complementary Metal Oxide Semiconductor (CMOS) technology has rapidly progressed, an image sensing device using CMOS technology (which is referred to as a CMOS image sensing device, hereinafter) developed. Compared to typical Charge Coupled Device (CCD) technology, the CMOS image sensing device has an advantage in that analog and digital control circuits may be directly implemented as an integrated circuit (IC) on a single chip.
A CMOS image sensing device has as many comparators as the number of columns in its pixel array. The comparators convert pixel signals outputted from pixels arranged in each row into digital signals. The comparator compares the pixel signal with a ramp signal to output the digital signal that is stored as an image.
FIG. 1 is a block diagram illustrating a layout of a typical image sensing device.
Referring to FIG. 1, the image sensing device includes a pixel array AR having a plurality of pixels arranged in rows and columns. Using a simplified example for ease of explanation, the pixels of the pixel array AR are arranged in two rows ROW0 to ROW1 and four columns COL0 to COL3. A structure corresponding to each of the columns COL0 to COL3 will be described.
A first column path corresponding to the first column COL0 will be described next.
The first column path includes a first pixel storage unit MIMI0, a first transmission line CL0, a first comparison unit AMP0, a first input line IL0, a first feedback line FL0, a first amplification storage unit MIMO0, a first primary output line OTL0, and a first secondary output line OBL0. The first pixel storage unit MIMI0 stores a first pixel signal outputted from pixels Gr0 and B0 of a first column COL0. The first transmission line CL0 is extended in a column direction and transmits the first pixel signal outputted from the pixels Gr0 and B0 of the first column COL0 to the first pixel storage unit MIMI0. The first comparison unit AMP0 reads the first pixel signal stored in the first pixel storage unit MIMI0 and generates first differential read signals, which are digital signals. The first input line IL0 is extended in the column direction and transmits the first pixel signal stored in the first pixel storage unit MIMI0 to the first comparison unit AMP0. The first feedback line FL0 is extended in parallel with the first input line IL0 and feeds back a first primary read signal of the first differential read signals. The first amplification storage unit MIMO0 stores the first primary read signal. The first primary output line OTL0 is extended in the column direction and transmits the first primary read signal to the first amplification storage unit MIMO0. The first secondary output line OBL0 is extended in parallel with the first primary output line OTL0 and transmits a first secondary read signal of the first differential read signals to an internal circuit (not shown).
The first pixel storage unit MIMI0 is spaced apart from the pixels Gr0 and B0 of the first column COL0 in the column direction. The first comparison unit AMP0 is spaced apart from the first pixel storage unit MIMI0 in the column direction. The first amplification storage unit MIMO0 is spaced apart from the first comparison unit AMP0 in the column direction.
A second column path corresponding to a second column COL1 will be described next.
The second column path includes a second pixel storage unit MIMI1, a second transmission line CL1, a second comparison unit AMP1, a second input line IL1, a second feedback line FL1, a second amplification storage unit MIMO1, a second primary output line OTL1, and a second secondary output line OBL1. The second pixel storage unit MIMI1 stores a second pixel signal outputted from pixels R0 and Gb0 of a second column COL1. The second transmission line CL1 is extended in a column direction and transmits the second pixel signal outputted from the pixels R0 and Gb0 of the second column COL1 to the second pixel storage unit MIMI1. The second comparison unit AMP1 reads the second pixel signal stored in the second pixel storage unit MIMI1 and generates second differential read signals, which are digital signals. The second input line IL1 is extended in the column direction and transmits the second pixel signal stored in the second pixel storage unit MIMI1 to the second comparison unit AMP1. The second feedback line FL1 is extended in parallel with the second input line IL1 and feeds back a second primary read signal of the second differential read signals. The second amplification storage unit MIMO1 stores the second primary read signal. The second primary output line OTL1 is extended in the column direction and transmits the second primary read signal to the second amplification storage unit MIMO1. The second secondary output line OBL1 is extended in parallel with the second primary output line OTL1 and transmits a second secondary read signal of the second differential read signals to an internal circuit (not shown).
The second pixel storage unit MIMI1 is spaced apart from the pixels R0 and Gb0 of the second column COL1 in the column direction. The second comparison unit AMP1 is spaced apart from the second pixel storage unit MIMI1 in the column direction. The second amplification storage unit MIMO1 is spaced apart from the second comparison unit AMP1 in the column direction.
The first pixel storage unit MIMI0 and the second pixel storage unit MIMI1 are disposed in the column direction. The first comparison unit AMP0 and the second comparison unit AMP1 are disposed in a row direction. The first amplification storage unit MIMO0 and the second amplification storage unit MIMO1 are disposed in the column direction.
The disposition order of the first input line IL0 and the first feedback line FL0 is asymmetrical to that of the second input line IL1 and the second feedback line FL1. The disposition order of the first primary output line OTL0 and the first secondary output line OBL0 is asymmetrical to that of the second primary output line OTL1 and the second secondary output line OBL1. For example, the input lines IL0 and IL1 and the corresponding feedback lines FL0 and FL1 are sequentially disposed from the left side of the CMOS image sensing device while the primary output lines OTL0 and OTL1 and the corresponding secondary output lines OBL0 and OBL1 are sequentially disposed from the left side of the CMOS image sensing device.
Next, a third column path corresponding to a third column COL2 is described.
The third column path includes a third pixel storage unit MIMI2, a third transmission line CL2, a third comparison unit AMP2, a third input line IL2, a third feedback line FL2, a third amplification storage unit MIMO2, a third primary output line OTL2, and a third secondary output line OBL2. The third pixel storage unit MIMI2 stores a third pixel signal outputted from pixels Gr1 and B1 of a third column COL2. The third transmission line CL2 is extended in a column direction and transmits the third pixel signal outputted from the pixels Gr1 and B1 of the third column COL2 to the third pixel storage unit MIMI2. The third comparison unit AMP2 reads the third pixel signal stored in the third pixel storage unit MIMI2 and generates third differential read signals which are digital signals. The third input line IL2 is extended in the column direction and transmits the third pixel signal stored in the third pixel storage unit MIMI2 to the third comparison unit AMP2. The third feedback line FL2 is extended in parallel with the third input line IL2 and feeds back a third primary read signal of the third differential read signals. The third amplification storage unit MIMO2 stores the third primary read signal. The third primary output line OTL2 is extended in the column direction and transmits the third primary read signal to the third amplification storage unit MIMO2. The third secondary output line OBL2 is extended in parallel with the third primary output line OTL2 and transmits a third secondary read signal of the third differential read signals to an internal circuit (not shown).
The third pixel storage unit MIMI2 is spaced apart from the pixels Gr1 and B1 of the third column COL2 in the column direction. The third comparison unit AMP2 is spaced apart from the third pixel storage unit MIMI2 in the column direction. The third amplification storage unit MIMO2 is spaced apart from the third comparison unit AMP2 in the column direction.
Hereafter, a fourth column path corresponding to a fourth column COL3 is described.
The fourth column path includes a fourth pixel storage unit MIMI3, a fourth transmission line CL3, a fourth comparison unit AMP3, a fourth input line IL3, a fourth feedback line FL3, a fourth amplification storage unit MIMO3, a fourth primary output line OTL3, and a fourth secondary output line OBL3. The fourth pixel storage unit MIMI3 stores a fourth pixel signal outputted from pixels R1 and Gb1 of a fourth column COL3. The fourth transmission line CL3 is extended in a column direction and transmits the fourth pixel signal outputted from the pixels R1 and Gb1 of the fourth column COL3 to the fourth pixel storage unit MIMI3. The fourth comparison unit AMP3 reads the fourth pixel signal stored in the fourth pixel storage unit MIMI3 and generates fourth differential read signals, which are digital signals. The fourth input line IL3 is extended in the column direction and transmits the fourth pixel signal stored in the fourth pixel storage unit MIMI3 to the fourth comparison unit AMP3. The fourth feedback line FL3 is extended in parallel with the fourth input line IL3 and feeds back a fourth primary read signal of the fourth differential read signals. The fourth amplification storage unit MIMO3 stores the fourth primary read signal. The fourth primary output line OTL3 is extended in the column direction and transmits the fourth primary read signal to the fourth amplification storage unit MIMO3. The fourth secondary output line OBL3 is extended in parallel with the fourth primary output line OTL3 and transmits a fourth secondary read signal of the fourth differential read signals to an internal circuit (not shown).
The fourth pixel storage unit MIMI3 is disposed apart from the pixels R1 and Gb1 of the fourth column COL3 in the column direction. The fourth comparison unit AMP3 is disposed apart from the fourth pixel storage unit MIMI3 in the column direction. The fourth amplification storage unit MIMO3 is disposed apart from the fourth comparison unit AMP3 in the column direction.
The third pixel storage unit MIMI2 and the fourth pixel storage unit MIMI3 are disposed in the column direction. The third comparison unit AMP2 and the fourth comparison unit AMP3 are disposed in a row direction. The third amplification storage unit MIMO2 and the fourth amplification storage unit MIMO3 are disposed in the column direction.
The disposition order of the third input line IL2 and the third feedback line FL2 is asymmetrical to that of the fourth input line IL3 and the fourth feedback line FL3. The disposition order of the third primary output line OTL2 and the third secondary output line OBL2 is asymmetrical to that of the fourth primary output line OTL3 and the fourth secondary output line OBL3. For example, the input lines IL2 and IL3 and the corresponding feedback lines FL2 and FL3 are sequentially disposed from the left side of the CMOS image sensing device, and the primary output lines OTL2 and OTL3 and the corresponding secondary output lines OBL2 and OBL3 are sequentially disposed from the left side of the CMOS image sensing device.
A shielding line SL is extended in the column direction at an interval of two column paths in the image sensing device. In other words, the image sensing device includes a first shielding line SL between the first column path and a column path adjacent to a left side of the first column path (not shown), a second shielding line SL between the second column path and the third column path, and a third shielding line SL between the fourth column path and a column path adjacent to a right side of the fourth column path (not shown).
FIG. 2 is a circuit diagram illustrating in detail the column path described above. FIG. 2 illustrates only the first and second column paths corresponding to the first and second columns COL0 and COL1, respectively.
Referring to FIG. 2, the first column path includes the first pixel storage unit MIMI0, the first comparison unit AMP0, and the first amplification storage unit MIMO0. The first pixel storage unit MIMI0 includes a capacitor, and the first comparison unit AMP0 includes a differential amplifier, while the first amplification storage unit MIMO0 includes a capacitor. The first comparison unit AMP0 outputs first differential read signals Voutp0 and Voutn0 after drawing a comparison between a first ramp signal Vramp0 transmitted through a first standard line RL0 and a first pixel signal Vin0 transmitted through the first input line IL0. The first standard line RL0 is mentioned for a better understanding of the first comparison unit AMP0, but it is not shown in FIG. 1.
The first column path further includes a first feedback unit SW0. The first feedback unit SW0 is coupled between the first feedback line FL0 and the first input line IL0, and the first feedback unit SW0 applies the first primary read signal Voutp0 to the first pixel signal Vin0. The first feedback unit SW0 includes a switch for selectively connecting the first feedback line FL0 to the first input line IL0 in response to a control signal (not shown). The first feedback unit SW0 is described for better understanding of the feedback path, although it is not shown in FIG. 1.
The second column path includes the second pixel storage unit MIMI1, the second comparison unit AMP1, and the second amplification storage unit MIMO1. A description on a structure of the second column path is omitted herein because the structure of the second column path is the same as that of the first column path.
The operation of the image sensing device having the above-described structure will now be described.
The rows of pixels of a pixel array AR are sequentially selected and first to fourth pixel signals Vpx0, Vpx1, Vpx2 and Vpx3 outputted from the pixels of the selected row are transmitted through the first to fourth column paths, respectively. For example, when the first row ROW0 is selected, the first to fourth pixel signals Vpx0, Vpx1, Vpx2 and Vpx3 are outputted from the respective pixels Gr0, R0, Gr1 and R1 of the first row ROW0, and the first to fourth pixel signals Vpx0, Vpx1, Vpx2 and Vpx3 are transmitted through the first to fourth column paths, respectively.
The process of the first to fourth pixel signals Vpx0, Vpx1, Vpx2 and Vpx3 being transmitted through the first to fourth column paths, respectively, is as follows.
The first to fourth pixel storage units MIMI0, MIMI1, MIMI2 and MIMI3 store the first to fourth pixel signals Vpx0, Vpx1, Vpx2 and Vpx3 outputted from the pixel array AR. The first to fourth comparison units AMP0, AMP1, AMP2 and AMP3 generate the first to fourth differential read signals Voutp0 and Voutn0, Voutp1 and Voutn1, Voutp2 and Voutn2, and Voutp3 and Voutn3 in response to the first to fourth pixel signals Vin0, Vin1, Vin2 and Vin3 stored in the first to fourth pixel storage units MIMI0, MIMI1, MIMI2 and MIMI3. The first to fourth amplification storage units MIMO0, MIMO1, MIMO2 and MIMO3 store the first to fourth primary read signals Voutp0, Voutp1, Voutp2 and Voutp3. The first to fourth feedback units SW0, SW1, SW2 and SW3 apply the first to fourth primary read signals Voutp0, Voutp1, Voutp2 and Voutp3 to the first to fourth pixel signals Vin0, Vin1, Vin2 and Vin3 in response to the control signal (not shown).
The first to fourth pixel signals Vpx0, Vpx1, Vpx2 and Vpx3 outputted from the pixel array AR are transmitted to the first to fourth pixel storage units MIMI0, MIMI1, MIMI2 and MIMI3 through the first to fourth transmission lines CL0, CL1, CL2 and CL3. The first to fourth pixel signals Vin0, Vin1, Vin2 and Vin3 stored in the first to fourth pixel storage units MIMI0, MIMI1, MIMI2 and MIMI3 are transmitted to the first to fourth comparison units AMP0, AMP1, AMP2 and AMP3 through the first to fourth input lines IL0, IL1, IL2 and IL3. The first to fourth primary read signals Voutp0, Voutp1, Voutp2 and Voutp3 are transmitted to the first to fourth amplification storage units MIMO0, MIMO1, MIMO2 and MIMO3 through the first to fourth primary output lines OTL0, OTL1, OTL2 and OTL3, and simultaneously to the first to fourth feedback units SW0, SW1, SW2 and SW3 through the first to fourth feedback lines FL0, FL1, FL2 and FL3.
However, the image sensing device having the above-described structure may have the following concerns.
As the size of pixels in a pixel array AR becomes smaller due to technological advances, the pitch between column paths and the pitch between signal lines becomes narrow. This forms a parasitic capacitor and interference between the signal lines, i.e., a coupling effect, occurs. For example, as the first primary read signal Voutp0 and the second pixel signal Vin1 having different dynamic ranges are transmitted through the first feedback line FL0 and the second input line IL1, which are disposed adjacent to each other, a coupling effect occurs. As the first secondary read signal Voutn0 and the second primary read signal Voutp1, having different dynamic ranges, are transmitted through the first secondary output line OBL0 and the second primary output line OTL1, which are disposed adjacent to each other, the coupling effect occurs (refer to FIG. 1). As the pitch between the column paths and the pitch between the signal lines becomes narrow, the extent of the coupling may gradually increase.
The surest way to prevent the signal line coupling is through the shielding line SL. However, there is a limitation in preventing coupling through the shielding line SL because the conditions for forming the shielding line SL are worse as the space becomes narrower.